1. Field of the Invention
The present invention is related to a fluorine treatment to shape the electric field in electron devices, passivate dislocations and point defects, and enhance the luminescence efficiency of optical devices, as well as manufacturing methods to obtain a high power field effect transistor without degradation in its high frequency performance.
2. Description of the Related Art
(Note: This application references a number of different publications and patents as indicated throughout the specification by one or more reference numbers within brackets, e.g., [x]. A list of these different publications and patents ordered according to these reference numbers can be found below in the section entitled “References.” Each of these publications and patents is incorporated by reference herein.)
The ability to locally change the electric field distribution can substantially improve the performance of different kinds of devices, for example, field effect transistors, high electron mobility transistors (HEMTs), light emitting diodes (LEDs), and ultraviolet detectors. In a standard AlGaN/GaN HEMT, for example, the electric field peaks at the drain side of the gate and consequently, the drain side of the gate constitutes the weak point through which breakdown occurs due to impact ionization.
Field effect transistors are commonly used as power amplifier devices. In power amplifiers, the maximum output power is proportional to the maximum current of the device and to the maximum voltage swing at the drain electrode. The maximum current is limited by material parameters, such as electron mobility and carrier density, while the voltage swing is, in first approximation, limited by the breakdown voltage of the device. In order to maximize the output power of a transistor, both the drain current and the voltage swing need to be increased.
There are different methods to increase the breakdown voltage of field effect transistors. One way is to limit the maximum drain current of the device, as shown for example, in [1]. Unfortunately, this method is not suited for high power applications, as the output power that results from this trade-off of current versus voltage is roughly constant.
A second method to increase the breakdown voltage was presented by Mishra et al [2]. In GaAs devices, the gate leakage has been identified as the main cause for the reduction of the breakdown voltage. In this method, Mishra et al. used a thin electron trap layer, on the surface of the device, to trap the electrons which flow on the surface between the drain and the gate [2]. This trap reduces the gate leakage, improving the breakdown voltage of the devices.
The other methods to increase the breakdown voltage of the device are based on reducing the peak electric field under the gate. Normally, the main voltage drop in the channel of field effect transistors occurs in a very confined region of about 50 nm at the drain side of the gate.
FIG. 1 shows how the main voltage drop in the channel of field effect transistors occurs in a very confined region of about 50 nm at the drain side of the gate, causing the electric field to peak in this confined region and reach very high values, typically greater than 100 KV/cm. FIG. 1 is a schematic of an AlGaN/GaN HEMT, comprising a source (100), drain (101), gate (102) and channel (103), superimposed on a graph illustrating the typical electric field profile in the channel (103). In this example, the drain source voltage (VDS) is 10 V and the gate-source voltage (VGS) is −6 V. When the drain voltage is increased, the peak electric field increases as well, and at a certain level of the drain voltage, the breakdown electric field is reached. At that point the transistor enters in breakdown regime and impact ionization of the carriers occurs, leading to increased leakage current and ultimately to the destruction of the device.
In order to increase the breakdown voltage, the electric field needs to be spread out, for example by an additional 50-100 nm towards the drain side of the gate. As the integral of the longitudinal electric field over the channel length is equal to the applied drain voltage, spreading out the electric field will reduce the peak electric field, in order to keep the area constant (i.e. the drain voltage does not change). Therefore, a higher drain voltage is needed to reach the breakdown electric field, which will increase the maximum output power.
Two main options to shape the electric field at the drain side of the gate are described in the literature. On one hand, recess engineering has proven to be a useful technique for shaping the electric field. The main idea behind multiple recess engineering is to increase the breakdown voltage of the devices, by reducing the charge density in the drain access region of the transistor [3,4]. In this technique, the device surface is brought closer to the channel by recessing the barrier layer, so that the surface potential will partially deplete the channel, and spread the electric field next to the gate, thereby reducing the peak value of the electric field.
However, the recess engineering method presents several important problems. First, it introduces parasitic resistances that will harm the frequency performance of the device. In particular, the method increases the drain access resistance, which in turn decreases the high frequency performance of the device. Second, to allow a controlled recess at the drain side of the gate, wet etching is normally used. This wet etch is not available for many semiconductor families, such as the nitrides for example. Third, the use of recesses in the access region decreases the distance between the channel and the surface of the semiconductor. This is likely to introduce dispersion in nitride-based devices, due to the higher effect of surface traps when they are close to the channel. Finally, another problem of multiple recesses is that the dry etch induces damage into the semiconductor that significantly increases the gate leakage of the devices.
The second technique involves the use of field plated structures, like the one shown in FIG. 2, to achieve electric field shaping. FIG. 2 is a schematic of a HEMT comprising a field plate structure (FP) (200), source (201), gate (202), drain (203), silicon nitride layer (204), AlGaN layer (205), and GaN layer (206). In this kind of device, the field plate structure (200), which can be connected to the source (201), to the gate (202), left floating or connected to an arbitrary voltage source, will modulate the carrier density at the drain side of the gate. The modulation will change the electric field in the drain region of the device by reducing its peak value at the gate edge. In this way, the breakdown voltage will be increased [5,6].
However, this second approach has the problem of significantly increasing the parasitic capacitances of the device. FIG. 3 shows how, in a transistor, as the thickness of the silicon nitride layer is increased, and when the FP is added to transistor, there is a parasitic increase in the gate-drain capacitance Cgd. The increase is independent of the length of the gate LG, at least in the range 50-250 nm. This increase in Cgd causes a reduction in the maximum frequency at which the transistor can operate. Therefore, this method is not a good option for high frequency devices [5,6], for example, high power devices operating at frequencies higher than 20 GHz. Furthermore, field plates require at least one additional lithography and metal evaporation process step. Although a transistor was used as an example, the parasitic increase in capacitance is also present in other similar devices.
What is needed, therefore, are improved techniques for locally changing the electric field distribution. The present invention satisfies these needs. In this document, new techniques to increase the breakdown voltage of field effect transistors, without degrading the maximum available current or the high frequency performance will be described. These new methods are based on the trap-related dispersion present in many semiconductors, especially in nitrides, due to surface states, and on the introduction of fixed charge into the devices.